/* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware driver * * Copyright (C) 2018-2019 Xilinx, Inc. */ #ifndef _ZYNQMP_FIRMWARE_H_ #define _ZYNQMP_FIRMWARE_H_ enum pm_api_id { PM_GET_API_VERSION = 1, PM_SET_CONFIGURATION = 2, PM_GET_NODE_STATUS = 3, PM_GET_OPERATING_CHARACTERISTIC = 4, PM_REGISTER_NOTIFIER = 5, /* API for suspending */ PM_REQUEST_SUSPEND = 6, PM_SELF_SUSPEND = 7, PM_FORCE_POWERDOWN = 8, PM_ABORT_SUSPEND = 9, PM_REQUEST_WAKEUP = 10, PM_SET_WAKEUP_SOURCE = 11, PM_SYSTEM_SHUTDOWN = 12, PM_REQUEST_NODE = 13, PM_RELEASE_NODE = 14, PM_SET_REQUIREMENT = 15, PM_SET_MAX_LATENCY = 16, /* Direct control API functions: */ PM_RESET_ASSERT = 17, PM_RESET_GET_STATUS = 18, PM_MMIO_WRITE = 19, PM_MMIO_READ = 20, PM_PM_INIT_FINALIZE = 21, PM_FPGA_LOAD = 22, PM_FPGA_GET_STATUS = 23, PM_GET_CHIPID = 24, /* ID 25 is been used by U-Boot to process secure boot images */ /* Secure library generic API functions */ PM_SECURE_SHA = 26, PM_SECURE_RSA = 27, PM_PINCTRL_REQUEST = 28, PM_PINCTRL_RELEASE = 29, PM_PINCTRL_GET_FUNCTION = 30, PM_PINCTRL_SET_FUNCTION = 31, PM_PINCTRL_CONFIG_PARAM_GET = 32, PM_PINCTRL_CONFIG_PARAM_SET = 33, PM_IOCTL = 34, PM_QUERY_DATA = 35, PM_CLOCK_ENABLE = 36, PM_CLOCK_DISABLE = 37, PM_CLOCK_GETSTATE = 38, PM_CLOCK_SETDIVIDER = 39, PM_CLOCK_GETDIVIDER = 40, PM_CLOCK_SETRATE = 41, PM_CLOCK_GETRATE = 42, PM_CLOCK_SETPARENT = 43, PM_CLOCK_GETPARENT = 44, PM_SECURE_IMAGE = 45, PM_FPGA_READ = 46, PM_SECURE_AES = 47, PM_CLOCK_PLL_GETPARAM = 49, /* PM_REGISTER_ACCESS API */ PM_REGISTER_ACCESS = 52, PM_EFUSE_ACCESS = 53, PM_FEATURE_CHECK = 63, PM_API_MAX, }; enum pm_node_id { NODE_UNKNOWN = 0, NODE_APU = 1, NODE_APU_0 = 2, NODE_APU_1 = 3, NODE_APU_2 = 4, NODE_APU_3 = 5, NODE_RPU = 6, NODE_RPU_0 = 7, NODE_RPU_1 = 8, NODE_PLD = 9, NODE_FPD = 10, NODE_OCM_BANK_0 = 11, NODE_OCM_BANK_1 = 12, NODE_OCM_BANK_2 = 13, NODE_OCM_BANK_3 = 14, NODE_TCM_0_A = 15, NODE_TCM_0_B = 16, NODE_TCM_1_A = 17, NODE_TCM_1_B = 18, NODE_L2 = 19, NODE_GPU_PP_0 = 20, NODE_GPU_PP_1 = 21, NODE_USB_0 = 22, NODE_USB_1 = 23, NODE_TTC_0 = 24, NODE_TTC_1 = 25, NODE_TTC_2 = 26, NODE_TTC_3 = 27, NODE_SATA = 28, NODE_ETH_0 = 29, NODE_ETH_1 = 30, NODE_ETH_2 = 31, NODE_ETH_3 = 32, NODE_UART_0 = 33, NODE_UART_1 = 34, NODE_SPI_0 = 35, NODE_SPI_1 = 36, NODE_I2C_0 = 37, NODE_I2C_1 = 38, NODE_SD_0 = 39, NODE_SD_1 = 40, NODE_DP = 41, NODE_GDMA = 42, NODE_ADMA = 43, NODE_NAND = 44, NODE_QSPI = 45, NODE_GPIO = 46, NODE_CAN_0 = 47, NODE_CAN_1 = 48, NODE_EXTERN = 49, NODE_APLL = 50, NODE_VPLL = 51, NODE_DPLL = 52, NODE_RPLL = 53, NODE_IOPLL = 54, NODE_DDR = 55, NODE_IPI_APU = 56, NODE_IPI_RPU_0 = 57, NODE_GPU = 58, NODE_PCIE = 59, NODE_PCAP = 60, NODE_RTC = 61, NODE_LPD = 62, NODE_VCU = 63, NODE_IPI_RPU_1 = 64, NODE_IPI_PL_0 = 65, NODE_IPI_PL_1 = 66, NODE_IPI_PL_2 = 67, NODE_IPI_PL_3 = 68, NODE_PL = 69, NODE_GEM_TSU = 70, NODE_SWDT_0 = 71, NODE_SWDT_1 = 72, NODE_CSU = 73, NODE_PJTAG = 74, NODE_TRACE = 75, NODE_TESTSCAN = 76, NODE_PMU = 77, NODE_MAX = 78, }; enum tap_delay_type { PM_TAPDELAY_INPUT = 0, PM_TAPDELAY_OUTPUT = 1, }; enum dll_reset_type { PM_DLL_RESET_ASSERT = 0, PM_DLL_RESET_RELEASE = 1, PM_DLL_RESET_PULSE = 2, }; enum ospi_mux_select_type { PM_OSPI_MUX_SEL_DMA, PM_OSPI_MUX_SEL_LINEAR, PM_OSPI_MUX_GET_MODE, }; enum pm_query_id { PM_QID_INVALID = 0, PM_QID_CLOCK_GET_NAME = 1, PM_QID_CLOCK_GET_TOPOLOGY = 2, PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, PM_QID_CLOCK_GET_PARENTS = 4, PM_QID_CLOCK_GET_ATTRIBUTES = 5, PM_QID_PINCTRL_GET_NUM_PINS = 6, PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7, PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8, PM_QID_PINCTRL_GET_FUNCTION_NAME = 9, PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10, PM_QID_PINCTRL_GET_PIN_GROUPS = 11, PM_QID_CLOCK_GET_NUM_CLOCKS = 12, PM_QID_CLOCK_GET_MAX_DIVISOR = 13, }; enum pm_pinctrl_config_param { PM_PINCTRL_CONFIG_SLEW_RATE = 0, PM_PINCTRL_CONFIG_BIAS_STATUS = 1, PM_PINCTRL_CONFIG_PULL_CTRL = 2, PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3, PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4, PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5, PM_PINCTRL_CONFIG_TRI_STATE = 6, PM_PINCTRL_CONFIG_MAX = 7, }; enum pm_pinctrl_slew_rate { PM_PINCTRL_SLEW_RATE_FAST = 0, PM_PINCTRL_SLEW_RATE_SLOW = 1, }; enum pm_pinctrl_bias_status { PM_PINCTRL_BIAS_DISABLE = 0, PM_PINCTRL_BIAS_ENABLE = 1, }; enum pm_pinctrl_pull_ctrl { PM_PINCTRL_BIAS_PULL_DOWN = 0, PM_PINCTRL_BIAS_PULL_UP = 1, }; enum pm_pinctrl_schmitt_cmos { PM_PINCTRL_INPUT_TYPE_CMOS = 0, PM_PINCTRL_INPUT_TYPE_SCHMITT = 1, }; enum pm_pinctrl_drive_strength { PM_PINCTRL_DRIVE_STRENGTH_2MA = 0, PM_PINCTRL_DRIVE_STRENGTH_4MA = 1, PM_PINCTRL_DRIVE_STRENGTH_8MA = 2, PM_PINCTRL_DRIVE_STRENGTH_12MA = 3, }; enum pm_pinctrl_tri_state { PM_PINCTRL_TRI_STATE_DISABLE = 0, PM_PINCTRL_TRI_STATE_ENABLE = 1, }; enum zynqmp_pm_reset_action { PM_RESET_ACTION_RELEASE = 0, PM_RESET_ACTION_ASSERT = 1, PM_RESET_ACTION_PULSE = 2, }; enum zynqmp_pm_reset { ZYNQMP_PM_RESET_START = 1000, ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, ZYNQMP_PM_RESET_PCIE_CTRL = 1002, ZYNQMP_PM_RESET_DP = 1003, ZYNQMP_PM_RESET_SWDT_CRF = 1004, ZYNQMP_PM_RESET_AFI_FM5 = 1005, ZYNQMP_PM_RESET_AFI_FM4 = 1006, ZYNQMP_PM_RESET_AFI_FM3 = 1007, ZYNQMP_PM_RESET_AFI_FM2 = 1008, ZYNQMP_PM_RESET_AFI_FM1 = 1009, ZYNQMP_PM_RESET_AFI_FM0 = 1010, ZYNQMP_PM_RESET_GDMA = 1011, ZYNQMP_PM_RESET_GPU_PP1 = 1012, ZYNQMP_PM_RESET_GPU_PP0 = 1013, ZYNQMP_PM_RESET_GPU = 1014, ZYNQMP_PM_RESET_GT = 1015, ZYNQMP_PM_RESET_SATA = 1016, ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, ZYNQMP_PM_RESET_APU_L2 = 1021, ZYNQMP_PM_RESET_ACPU3 = 1022, ZYNQMP_PM_RESET_ACPU2 = 1023, ZYNQMP_PM_RESET_ACPU1 = 1024, ZYNQMP_PM_RESET_ACPU0 = 1025, ZYNQMP_PM_RESET_DDR = 1026, ZYNQMP_PM_RESET_APM_FPD = 1027, ZYNQMP_PM_RESET_SOFT = 1028, ZYNQMP_PM_RESET_GEM0 = 1029, ZYNQMP_PM_RESET_GEM1 = 1030, ZYNQMP_PM_RESET_GEM2 = 1031, ZYNQMP_PM_RESET_GEM3 = 1032, ZYNQMP_PM_RESET_QSPI = 1033, ZYNQMP_PM_RESET_UART0 = 1034, ZYNQMP_PM_RESET_UART1 = 1035, ZYNQMP_PM_RESET_SPI0 = 1036, ZYNQMP_PM_RESET_SPI1 = 1037, ZYNQMP_PM_RESET_SDIO0 = 1038, ZYNQMP_PM_RESET_SDIO1 = 1039, ZYNQMP_PM_RESET_CAN0 = 1040, ZYNQMP_PM_RESET_CAN1 = 1041, ZYNQMP_PM_RESET_I2C0 = 1042, ZYNQMP_PM_RESET_I2C1 = 1043, ZYNQMP_PM_RESET_TTC0 = 1044, ZYNQMP_PM_RESET_TTC1 = 1045, ZYNQMP_PM_RESET_TTC2 = 1046, ZYNQMP_PM_RESET_TTC3 = 1047, ZYNQMP_PM_RESET_SWDT_CRL = 1048, ZYNQMP_PM_RESET_NAND = 1049, ZYNQMP_PM_RESET_ADMA = 1050, ZYNQMP_PM_RESET_GPIO = 1051, ZYNQMP_PM_RESET_IOU_CC = 1052, ZYNQMP_PM_RESET_TIMESTAMP = 1053, ZYNQMP_PM_RESET_RPU_R50 = 1054, ZYNQMP_PM_RESET_RPU_R51 = 1055, ZYNQMP_PM_RESET_RPU_AMBA = 1056, ZYNQMP_PM_RESET_OCM = 1057, ZYNQMP_PM_RESET_RPU_PGE = 1058, ZYNQMP_PM_RESET_USB0_CORERESET = 1059, ZYNQMP_PM_RESET_USB1_CORERESET = 1060, ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, ZYNQMP_PM_RESET_USB0_APB = 1063, ZYNQMP_PM_RESET_USB1_APB = 1064, ZYNQMP_PM_RESET_IPI = 1065, ZYNQMP_PM_RESET_APM_LPD = 1066, ZYNQMP_PM_RESET_RTC = 1067, ZYNQMP_PM_RESET_SYSMON = 1068, ZYNQMP_PM_RESET_AFI_FM6 = 1069, ZYNQMP_PM_RESET_LPD_SWDT = 1070, ZYNQMP_PM_RESET_FPD = 1071, ZYNQMP_PM_RESET_RPU_DBG1 = 1072, ZYNQMP_PM_RESET_RPU_DBG0 = 1073, ZYNQMP_PM_RESET_DBG_LPD = 1074, ZYNQMP_PM_RESET_DBG_FPD = 1075, ZYNQMP_PM_RESET_APLL = 1076, ZYNQMP_PM_RESET_DPLL = 1077, ZYNQMP_PM_RESET_VPLL = 1078, ZYNQMP_PM_RESET_IOPLL = 1079, ZYNQMP_PM_RESET_RPLL = 1080, ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, ZYNQMP_PM_RESET_RPU_LS = 1113, ZYNQMP_PM_RESET_PS_ONLY = 1114, ZYNQMP_PM_RESET_PL = 1115, ZYNQMP_PM_RESET_PS_PL0 = 1116, ZYNQMP_PM_RESET_PS_PL1 = 1117, ZYNQMP_PM_RESET_PS_PL2 = 1118, ZYNQMP_PM_RESET_PS_PL3 = 1119, ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 }; enum pm_ioctl_id { IOCTL_GET_RPU_OPER_MODE = 0, IOCTL_SET_RPU_OPER_MODE = 1, IOCTL_RPU_BOOT_ADDR_CONFIG = 2, IOCTL_TCM_COMB_CONFIG = 3, IOCTL_SET_TAPDELAY_BYPASS = 4, IOCTL_SET_SGMII_MODE = 5, IOCTL_SD_DLL_RESET = 6, IOCTL_SET_SD_TAPDELAY = 7, IOCTL_SET_PLL_FRAC_MODE = 8, IOCTL_GET_PLL_FRAC_MODE = 9, IOCTL_SET_PLL_FRAC_DATA = 10, IOCTL_GET_PLL_FRAC_DATA = 11, IOCTL_WRITE_GGS = 12, IOCTL_READ_GGS = 13, IOCTL_WRITE_PGGS = 14, IOCTL_READ_PGGS = 15, /* IOCTL for ULPI reset */ IOCTL_ULPI_RESET = 16, /* Set healthy bit value*/ IOCTL_SET_BOOT_HEALTH_STATUS = 17, IOCTL_AFI = 18, /* Probe counter read/write */ IOCTL_PROBE_COUNTER_READ = 19, IOCTL_PROBE_COUNTER_WRITE = 20, IOCTL_OSPI_MUX_SELECT = 21, /* IOCTL for USB power request */ IOCTL_USB_SET_STATE = 22, /* IOCTL to get last reset reason */ IOCTL_GET_LAST_RESET_REASON = 23, /* AIE ISR Clear */ IOCTL_AIE_ISR_CLEAR = 24, /* Register SGI to ATF */ IOCTL_REGISTER_SGI = 25, /* Runtime feature configuration */ IOCTL_SET_FEATURE_CONFIG = 26, IOCTL_GET_FEATURE_CONFIG = 27, /* IOCTL for Secure Read/Write Interface */ IOCTL_READ_REG = 28, IOCTL_MASK_WRITE_REG = 29, /* Dynamic SD/GEM/USB configuration */ IOCTL_SET_SD_CONFIG = 30, IOCTL_SET_GEM_CONFIG = 31, IOCTL_SET_USB_CONFIG = 32, /* AIE/AIEML Operations */ IOCTL_AIE_OPS = 33, /* IOCTL to get default/current QoS */ IOCTL_GET_QOS = 34, }; enum pm_sd_config_type { SD_CONFIG_EMMC_SEL = 1, /* To set SD_EMMC_SEL in CTRL_REG_SD */ SD_CONFIG_BASECLK = 2, /* To set SD_BASECLK in SD_CONFIG_REG1 */ SD_CONFIG_8BIT = 3, /* To set SD_8BIT in SD_CONFIG_REG2 */ SD_CONFIG_FIXED = 4, /* To set fixed config registers */ }; enum pm_gem_config_type { GEM_CONFIG_SGMII_MODE = 1, /* To set GEM_SGMII_MODE in GEM_CLK_CTRL */ GEM_CONFIG_FIXED = 2, /* To set fixed config registers */ }; #define PM_SIP_SVC 0xc2000000 #define ZYNQMP_PM_VERSION_MAJOR 1 #define ZYNQMP_PM_VERSION_MINOR 0 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF #define ZYNQMP_PM_VERSION \ ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ ZYNQMP_PM_VERSION_MINOR) #define ZYNQMP_PM_VERSION_INVALID ~0 #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) #define PMIO_NODE_ID_BASE 0x1410801B /* * Return payload size * Not every firmware call expects the same amount of return bytes, however the * firmware driver always copies 5 bytes from RX buffer to the ret_payload * buffer. Therefore allocating with this defined value is recommended to avoid * overflows. */ #define PAYLOAD_ARG_CNT 5U unsigned int zynqmp_firmware_version(void); int zynqmp_pmufw_node(u32 id); int zynqmp_pmufw_config_close(void); int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value); int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_mmio_read(const u32 address, u32 *value); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_pm_feature(const u32 api_id); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U #define PM_CONFIG_OBJECT_TYPE_OVERLAY 0x2U /* Section Id */ #define PM_CONFIG_SLAVE_SECTION_ID 0x102U #define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U /* Flag Option */ #define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U #define PM_MASTER_USING_SLAVE_MASK 0x2U /* IPI Mask for Master */ #define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001 #define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100 #define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200 enum zynqmp_pm_request_ack { ZYNQMP_PM_REQUEST_ACK_NO = 1, ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2, ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3, }; /* Node capabilities */ #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U #define ZYNQMP_PM_MAX_QOS 100U /* Firmware feature check version mask */ #define FIRMWARE_VERSION_MASK GENMASK(15, 0) /* PM API versions */ #define PM_API_VERSION_2 2 #define PM_PINCTRL_PARAM_SET_VERSION 2 struct zynqmp_ipi_msg { size_t len; u32 *buf; }; #endif /* _ZYNQMP_FIRMWARE_H_ */