/* SPDX-License-Identifier: GPL-2.0+ */ /* * Configuration settings for the Espresso7420 board. * Copyright (C) 2016 Samsung Electronics * Thomas Abraham */ #ifndef __CONFIG_EXYNOS7420_COMMON_H #define __CONFIG_EXYNOS7420_COMMON_H #include /* get chip and board defs */ #include /* Miscellaneous configurable options */ /* select serial console configuration */ #define CPU_RELEASE_ADDR secondary_boot_addr /* select serial console configuration */ #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE /* Configuration of ENV Blocks */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ #ifndef MEM_LAYOUT_ENV_SETTINGS #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "kernel_addr_r=0x42000000\0" \ "fdt_addr_r=0x43000000\0" \ "ramdisk_addr_r=0x43300000\0" \ "scriptaddr=0x50000000\0" \ "pxefile_addr_r=0x51000000\0" #endif #ifndef EXYNOS_DEVICE_SETTINGS #define EXYNOS_DEVICE_SETTINGS \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" #endif #ifndef EXYNOS_FDTFILE_SETTING #define EXYNOS_FDTFILE_SETTING #endif #define CFG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS \ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS #endif /* __CONFIG_EXYNOS7420_COMMON_H */