// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2006-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. */ #include #include #include #include #include static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; static struct mtd_info *mtd; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ CFG_SYS_NAND_ECCSIZE) #define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512) /* * NAND command for small page NAND devices (512) */ static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; while (!this->dev_ready(mtd)) ; /* Begin command latch cycle */ this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Set ALE and clear CLE to start address cycle */ /* Column address */ this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE); this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */ this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, NAND_CTRL_ALE); /* A[24:17] */ /* Latch in address */ this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ while (!this->dev_ready(mtd)) ; return 0; } #else /* * NAND command for large page NAND devices (2k) */ static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; while (!this->dev_ready(mtd)) ; /* Emulate NAND_CMD_READOOB */ if (cmd == NAND_CMD_READOOB) { offs += CONFIG_SYS_NAND_PAGE_SIZE; cmd = NAND_CMD_READ0; } /* Shift the offset from byte addressing to word addressing. */ if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; /* Begin command latch cycle */ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Set ALE and clear CLE to start address cycle */ /* Column address */ hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ /* Row address */ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); /* A[27:20] */ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE /* One more address cycle for devices > 128MiB */ hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); /* A[31:28] */ #endif /* Latch in address */ hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ while (!this->dev_ready(mtd)) ; return 0; } #endif static int nand_is_bad_block(int block) { struct nand_chip *this = mtd_to_nand(mtd); u_char bb_data[2]; nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); /* * Read one byte (or two if it's a 16 bit chip). */ if (this->options & NAND_BUSWIDTH_16) { this->read_buf(mtd, bb_data, 2); if (bb_data[0] != 0xff || bb_data[1] != 0xff) return 1; } else { this->read_buf(mtd, bb_data, 1); if (bb_data[0] != 0xff) return 1; } return 0; } #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST) static int nand_read_page(int block, int page, uchar *dst) { struct nand_chip *this = mtd_to_nand(mtd); u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; int eccsize = CFG_SYS_NAND_ECCSIZE; int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; uint8_t *p = dst; nand_command(block, page, 0, NAND_CMD_READOOB); this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); nand_command(block, page, 0, NAND_CMD_READ0); /* Pick the ECC bytes out of the oob data */ for (i = 0; i < ECCTOTAL; i++) ecc_code[i] = oob_data[nand_ecc_pos[i]]; for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { this->ecc.hwctl(mtd, NAND_ECC_READ); this->read_buf(mtd, p, eccsize); this->ecc.calculate(mtd, p, &ecc_calc[i]); this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); } return 0; } #else static int nand_read_page(int block, int page, void *dst) { struct nand_chip *this = mtd_to_nand(mtd); u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; int eccsize = CFG_SYS_NAND_ECCSIZE; int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; uint8_t *p = dst; nand_command(block, page, 0, NAND_CMD_READ0); for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { if (this->ecc.mode != NAND_ECC_SOFT) this->ecc.hwctl(mtd, NAND_ECC_READ); this->read_buf(mtd, p, eccsize); this->ecc.calculate(mtd, p, &ecc_calc[i]); } this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); /* Pick the ECC bytes out of the oob data */ for (i = 0; i < ECCTOTAL; i++) ecc_code[i] = oob_data[nand_ecc_pos[i]]; eccsteps = ECCSTEPS; p = dst; for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { /* No chance to do something with the possible error message * from correct_data(). We just hope that all possible errors * are corrected by this routine. */ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); } return 0; } #endif /* nand_init() - initialize data to make nand usable by SPL */ void nand_init(void) { /* * Init board specific nand support */ mtd = nand_to_mtd(&nand_chip); nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE; board_nand_init(&nand_chip); #ifdef CONFIG_SPL_NAND_SOFTECC if (nand_chip.ecc.mode == NAND_ECC_SOFT) { nand_chip.ecc.calculate = nand_calculate_ecc; nand_chip.ecc.correct = nand_correct_data; } #endif if (nand_chip.select_chip) nand_chip.select_chip(mtd, 0); } /* Unselect after operation */ void nand_deselect(void) { if (nand_chip.select_chip) nand_chip.select_chip(mtd, -1); } #include "nand_spl_loaders.c"