// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2021 Linumiz * Author: Navin Sankar Velliangiri */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = imx_ddr_size(); return 0; } #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ PAD_CTL_HYS) static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } int board_early_init_f(void) { setup_iomux_uart(); return 0; } #ifdef CONFIG_FEC_MXC static int setup_fec(int fec_id) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; if (fec_id == 0) { /* * Use 50MHz anatop loopback REF_CLK1 for ENET1, * clear gpr1[13], set gpr1[17]. */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); } else { /* * Use 50MHz anatop loopbak REF_CLK2 for ENET2, * clear gpr1[14], set gpr1[18]. */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); } ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); if (ret) return ret; enable_enet_clk(1); return 0; } int board_phy_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); if (phydev->drv->config) phydev->drv->config(phydev); return 0; } #endif int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC setup_fec(CFG_FEC_ENET_DEV); #endif return 0; } int checkboard(void) { printf("Board: Seeed NPi i.MX6ULL Dev Board\n"); return 0; }