// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "../common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = imx_ddr_size(); return 0; } static iomux_v3_cfg_t const wdog_pads[] = { MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), }; #ifdef CONFIG_DM_PMIC_PFUZE100 int power_init_board(void) { struct udevice *dev; int ret; u32 dev_id, rev_id, i; u32 switch_num = 6; u32 offset = PFUZE100_SW1CMODE; ret = pmic_get("pfuze100@8", &dev); if (ret == -ENODEV) return 0; if (ret != 0) return ret; dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); rev_id = pmic_reg_read(dev, PFUZE100_REVID); printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* Init mode to APS_PFM */ pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); for (i = 0; i < switch_num - 1; i++) pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); /* set SW1AB staby volatage 0.975V */ pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); /* set SW1C staby volatage 0.975V */ pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); return 0; } #endif int board_early_init_f(void) { return 0; } int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; return 0; } int board_late_init(void) { imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); return 0; } int checkboard(void) { puts("Board: MX6SLL EVK\n"); return 0; } int board_mmc_get_env_dev(int devno) { return devno; } int mmc_map_to_kernel_blk(int devno) { return devno; }