// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2018 NXP */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "../common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) static iomux_v3_cfg_t const wdog_pads[] = { IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; static iomux_v3_cfg_t const uart_pads[] = { IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); return 0; } #ifdef CONFIG_FEC_MXC static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; /* Use 125M anatop REF_CLK1 for ENET1, not from external */ clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); return set_clk_enet(ENET_125MHZ); } int board_phy_config(struct phy_device *phydev) { /* enable rgmii rxc skew and phy mode select to RGMII copper */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); if (phydev->drv->config) phydev->drv->config(phydev); return 0; } #endif int board_init(void) { #ifdef CONFIG_FEC_MXC setup_fec(); #endif #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3) init_usb_clk(); #endif return 0; } int board_mmc_get_env_dev(int devno) { return devno; } int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "EVK"); env_set("board_rev", "iMX8MQ"); #endif return 0; }