// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2007-2008 * Stelian Pop * Lead Tech Design */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; /* ------------------------------------------------------------------------- */ /* * Miscelaneous platform dependent initialisations */ #ifdef CONFIG_CMD_NAND static void at91sam9263ek_nand_hw_init(void) { unsigned long csa; at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; writel(csa, &matrix->csa[0]); /* Enable CS3 */ /* Configure SMC CS3 for NAND/SmartMedia */ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), &smc->cs[3].setup); writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), &smc->cs[3].pulse); writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_MODE_DBW_8 | #endif AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); at91_periph_clk_enable(ATMEL_ID_PIOA); at91_periph_clk_enable(ATMEL_ID_PIOCDE); /* Configure RDY/BSY */ at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { at91_seriald_hw_init(); } #endif #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { return 0; } #endif int board_init(void) { /* arch number of AT91SAM9263EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; /* adress of boot parameters */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); #endif #ifdef CONFIG_USB_OHCI_NEW at91_uhp_hw_init(); #endif return 0; } int dram_init(void) { gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); return 0; } #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { } #endif