/* SPDX-License-Identifier: GPL-2.0+ */ /* * Taken from the linux kernel file of the same name * * (C) Copyright 2012 * Graeme Russ, */ #ifndef _ASM_X86_MSR_INDEX_H #define _ASM_X86_MSR_INDEX_H #ifndef __ASSEMBLY__ #include #endif /* CPU model specific register (MSR) numbers */ /* x86-64 specific MSRs */ #define MSR_EFER 0xc0000080 /* extended feature register */ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ /* EFER bits: */ #define _EFER_SCE 0 /* SYSCALL/SYSRET */ #define _EFER_LME 8 /* Long mode enable */ #define _EFER_LMA 10 /* Long mode active (read-only) */ #define _EFER_NX 11 /* No execute enable */ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ #define EFER_SCE (1<<_EFER_SCE) #define EFER_LME (1<<_EFER_LME) #define EFER_LMA (1<<_EFER_LMA) #define EFER_NX (1<<_EFER_NX) #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) /* Intel MSRs. Some also available on other CPUs */ #define MSR_PIC_MSG_CONTROL 0x2e #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_MTRR_CAP_MSR 0x0fe #define MSR_MTRR_CAP_SMRR (1 << 11) #define MSR_MTRR_CAP_WC (1 << 10) #define MSR_MTRR_CAP_FIX (1 << 8) #define MSR_MTRR_CAP_VCNT 0xff #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd #define MSR_NHM_PLATFORM_INFO 0x000000ce #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ #define PKG_C_STATE_LIMIT_C2_MASK BIT(1) /* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ #define CORE_C_STATE_LIMIT_C10_MASK 0x70 /* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ #define IO_MWAIT_REDIRECT_MASK BIT(10) /* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ #define CST_CFG_LOCK_MASK BIT(15) #define SINGLE_PCTL BIT(11) /* ACPI PMIO Offset to C-state register */ #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e #define MSR_POWER_MISC 0x00000120 #define FLUSH_DL1_L2 (1 << 8) #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) #define MSR_EMULATE_PM_TIMER 0x121 #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_VALUE 0x13 #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 #define MSR_IA32_SYSENTER_EIP 0x00000176 #define MSR_IA32_MCG_CAP 0x00000179 #define MSR_IA32_MCG_STATUS 0x0000017a #define MSR_IA32_MCG_CTL 0x0000017b #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) /* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) #define MSR_IA32_MISC_ENABLE 0x000001a0 /* MISC_ENABLE bits: architectural */ #define MISC_ENABLE_FAST_STRING BIT_ULL(0) #define MISC_ENABLE_TCC BIT_ULL(1) #define MISC_DISABLE_TURBO BIT_ULL(6) #define MISC_ENABLE_EMON BIT_ULL(7) #define MISC_ENABLE_BTS_UNAVAIL BIT_ULL(11) #define MISC_ENABLE_PEBS_UNAVAIL BIT_ULL(12) #define MISC_ENABLE_ENHANCED_SPEEDSTEP BIT_ULL(16) #define MISC_ENABLE_MWAIT BIT_ULL(18) #define MISC_ENABLE_LIMIT_CPUID BIT_ULL(22) #define MISC_ENABLE_XTPR_DISABLE BIT_ULL(23) #define MISC_ENABLE_XD_DISABLE BIT_ULL(34) /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ #define MISC_ENABLE_X87_COMPAT BIT_ULL(2) #define MISC_ENABLE_TM1 BIT_ULL(3) #define MISC_ENABLE_SPLIT_LOCK_DISABLE BIT_ULL(4) #define MISC_ENABLE_L3CACHE_DISABLE BIT_ULL(6) #define MISC_ENABLE_SUPPRESS_LOCK BIT_ULL(8) #define MISC_ENABLE_PREFETCH_DISABLE BIT_ULL(9) #define MISC_ENABLE_FERR BIT_ULL(10) #define MISC_ENABLE_FERR_MULTIPLEX BIT_ULL(10) #define MISC_ENABLE_TM2 BIT_ULL(13) #define MISC_ENABLE_ADJ_PREF_DISABLE BIT_ULL(19) #define MISC_ENABLE_SPEEDSTEP_LOCK BIT_ULL(20) #define MISC_ENABLE_L1D_CONTEXT BIT_ULL(24) #define MISC_ENABLE_DCU_PREF_DISABLE BIT_ULL(37) #define MISC_ENABLE_TURBO_DISABLE BIT_ULL(38) #define MISC_ENABLE_IP_PREF_DISABLE BIT_ULL(39) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_PREFETCH_CTL 0x1a4 #define PREFETCH_L1_DISABLE (1 << 0) #define PREFETCH_L2_DISABLE (1 << 2) #define MSR_OFFCORE_RSP_0 0x000001a6 #define MSR_OFFCORE_RSP_1 0x000001a7 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x000001ad #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 #define PACKAGE_THERM_STATUS_PROCHOT BIT(0) #define PACKAGE_THERM_STATUS_POWER_LIMIT BIT(10) #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 #define PACKAGE_THERM_INT_HIGH_ENABLE BIT(0) #define PACKAGE_THERM_INT_LOW_ENABLE BIT(1) #define PACKAGE_THERM_INT_PLN_ENABLE BIT(24) #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 #define MSR_IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x000001fc #define MSR_LBR_NHM_FROM 0x00000680 #define MSR_LBR_NHM_TO 0x000006c0 #define MSR_LBR_CORE_FROM 0x00000040 #define MSR_LBR_CORE_TO 0x00000060 #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 #define MSR_MTRRfix64K_00000 0x00000250 #define MSR_MTRRfix16K_80000 0x00000258 #define MSR_MTRRfix16K_A0000 0x00000259 #define MSR_MTRRfix4K_C0000 0x00000268 #define MSR_MTRRfix4K_C8000 0x00000269 #define MSR_MTRRfix4K_D0000 0x0000026a #define MSR_MTRRfix4K_D8000 0x0000026b #define MSR_MTRRfix4K_E0000 0x0000026c #define MSR_MTRRfix4K_E8000 0x0000026d #define MSR_MTRRfix4K_F0000 0x0000026e #define MSR_MTRRfix4K_F8000 0x0000026f #define MSR_MTRRdefType 0x000002ff #define MSR_IA32_CR_PAT 0x00000277 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db #define MSR_IA32_LASTBRANCHTOIP 0x000001dc #define MSR_IA32_LASTINTFROMIP 0x000001dd #define MSR_IA32_LASTINTTOIP 0x000001de /* DEBUGCTLMSR bits (others vary by model): */ #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ /* single-step on branches */ #define DEBUGCTLMSR_BTF (1UL << 1) #define DEBUGCTLMSR_TR (1UL << 6) #define DEBUGCTLMSR_BTS (1UL << 7) #define DEBUGCTLMSR_BTINT (1UL << 8) #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) #define MSR_IA32_POWER_CTL 0x000001fc #define MSR_IA32_MC0_CTL 0x00000400 #define MSR_IA32_MC0_STATUS 0x00000401 #define MSR_IA32_MC0_ADDR 0x00000402 #define MSR_IA32_MC0_MISC 0x00000403 /* C-state Residency Counters */ #define MSR_PKG_C3_RESIDENCY 0x000003f8 #define MSR_PKG_C6_RESIDENCY 0x000003f9 #define MSR_PKG_C7_RESIDENCY 0x000003fa #define MSR_CORE_C3_RESIDENCY 0x000003fc #define MSR_CORE_C6_RESIDENCY 0x000003fd #define MSR_CORE_C7_RESIDENCY 0x000003fe #define MSR_PKG_C2_RESIDENCY 0x0000060d #define MSR_PKG_C8_RESIDENCY 0x00000630 #define MSR_PKG_C9_RESIDENCY 0x00000631 #define MSR_PKG_C10_RESIDENCY 0x00000632 /* Run Time Average Power Limiting (RAPL) Interface */ #define MSR_PKG_POWER_SKU_UNIT 0x00000606 #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 #define IRTL_VALID (1 << 15) #define IRTL_1_NS (0 << 10) #define IRTL_32_NS (1 << 10) #define IRTL_1024_NS (2 << 10) #define IRTL_32768_NS (3 << 10) #define IRTL_1048576_NS (4 << 10) #define IRTL_33554432_NS (5 << 10) #define IRTL_RESPONSE_MASK (0x3ff) #define MSR_PKG_POWER_LIMIT 0x00000610 /* long duration in low dword, short duration in high dword */ #define PKG_POWER_LIMIT_MASK 0x7fff #define PKG_POWER_LIMIT_EN (1 << 15) #define PKG_POWER_LIMIT_CLAMP (1 << 16) #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK 0x7f /* * For Mobile, RAPL default PL1 time window value set to 28 seconds. * RAPL time window calculation defined as follows: * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. */ #define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e #define MSR_PKG_ENERGY_STATUS 0x00000611 #define MSR_PKG_PERF_STATUS 0x00000613 #define MSR_PKG_POWER_SKU 0x614 #define MSR_DRAM_POWER_LIMIT 0x00000618 #define MSR_DRAM_ENERGY_STATUS 0x00000619 #define MSR_DRAM_PERF_STATUS 0x0000061b #define MSR_DRAM_POWER_INFO 0x0000061c #define MSR_PP0_POWER_LIMIT 0x00000638 #define MSR_PP0_ENERGY_STATUS 0x00000639 #define MSR_PP0_POLICY 0x0000063a #define MSR_PP0_PERF_STATUS 0x0000063b #define MSR_PP1_POWER_LIMIT 0x00000640 #define MSR_PP1_ENERGY_STATUS 0x00000641 #define MSR_PP1_POLICY 0x00000642 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064c #define MSR_CORE_C1_RES 0x00000660 #define MSR_IACORE_RATIOS 0x0000066a #define MSR_IACORE_TURBO_RATIOS 0x0000066c #define MSR_IACORE_VIDS 0x0000066b #define MSR_IACORE_TURBO_VIDS 0x0000066d #define MSR_PKG_TURBO_CFG1 0x00000670 #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 #define MSR_CPU_THERM_CFG1 0x00000673 #define MSR_CPU_THERM_CFG2 0x00000674 #define MSR_CPU_THERM_SENS_CFG 0x00000675 #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) /* These are consecutive and not in the normal 4er MCE bank block */ #define MSR_IA32_MC0_CTL2 0x00000280 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) #define MSR_P6_PERFCTR0 0x000000c1 #define MSR_P6_PERFCTR1 0x000000c2 #define MSR_P6_EVNTSEL0 0x00000186 #define MSR_P6_EVNTSEL1 0x00000187 #define MSR_KNC_PERFCTR0 0x00000020 #define MSR_KNC_PERFCTR1 0x00000021 #define MSR_KNC_EVNTSEL0 0x00000028 #define MSR_KNC_EVNTSEL1 0x00000029 /* Alternative perfctr range with full access. */ #define MSR_IA32_PMC0 0x000004c1 /* AMD64 MSRs. Not complete. See the architecture manual for a more complete list. */ #define MSR_AMD64_PATCH_LEVEL 0x0000008b #define MSR_AMD64_TSC_RATIO 0xc0000104 #define MSR_AMD64_NB_CFG 0xc001001f #define MSR_AMD64_PATCH_LOADER 0xc0010020 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 #define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<