#ifndef __ASM_PPC_PROCESSOR_H #define __ASM_PPC_PROCESSOR_H /* * Default implementation of macro that returns current * instruction pointer ("program counter"). */ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) #include #include /* Machine State Register (MSR) Fields */ #ifdef CONFIG_PPC64BRIDGE #define MSR_SF (1<<63) #define MSR_ISF (1<<61) #endif /* CONFIG_PPC64BRIDGE */ #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ #define MSR_SPE (1<<25) /* Enable SPE(e500) */ #define MSR_POW (1<<18) /* Enable Power Management */ #define MSR_WE (1<<18) /* Wait State Enable */ #define MSR_TGPR (1<<17) /* TLB Update registers in use */ #define MSR_CE (1<<17) /* Critical Interrupt Enable */ #define MSR_ILE (1<<16) /* Interrupt Little Endian */ #define MSR_EE (1<<15) /* External Interrupt Enable */ #define MSR_PR (1<<14) /* Problem State / Privilege Level */ #define MSR_FP (1<<13) /* Floating Point enable */ #define MSR_ME (1<<12) /* Machine Check Enable */ #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ #define MSR_SE (1<<10) /* Single Step */ #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ #define MSR_BE (1<<9) /* Branch Trace */ #define MSR_DE (1<<9) /* Debug Exception Enable */ #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ #define MSR_IR (1<<5) /* Instruction Relocate */ #define MSR_IS (1<<5) /* Book E Instruction space */ #define MSR_DR (1<<4) /* Data Relocate */ #define MSR_DS (1<<4) /* Book E Data space */ #define MSR_PE (1<<3) /* Protection Enable */ #define MSR_PX (1<<2) /* Protection Exclusive Mode */ #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ #define MSR_RI (1<<1) /* Recoverable Exception */ #define MSR_LE (1<<0) /* Little Endian */ #define MSR_ MSR_ME|MSR_RI #ifndef CONFIG_E500 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR #else #define MSR_KERNEL MSR_ME #endif /* Floating Point Status and Control Register (FPSCR) Fields */ #define FPSCR_FX 0x80000000 /* FPU exception summary */ #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ #define FPSCR_VX 0x20000000 /* Invalid operation summary */ #define FPSCR_OX 0x10000000 /* Overflow exception summary */ #define FPSCR_UX 0x08000000 /* Underflow exception summary */ #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ #define FPSCR_XX 0x02000000 /* Inexact exception summary */ #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ #define FPSCR_FR 0x00040000 /* Fraction rounded */ #define FPSCR_FI 0x00020000 /* Fraction inexact */ #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ #define FPSCR_RN 0x00000003 /* FPU rounding control */ /* Special Purpose Registers (SPRNs)*/ #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ #ifdef CONFIG_BOOKE #define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ #endif #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ #else #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ #endif /* CONFIG_BOOKE */ #define SPRN_DAR 0x013 /* Data Address Register */ #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ #define DBCR_EDM 0x80000000 #define DBCR_IDM 0x40000000 #define DBCR_RST(x) (((x) & 0x3) << 28) #define DBCR_RST_NONE 0 #define DBCR_RST_CORE 1 #define DBCR_RST_CHIP 2 #define DBCR_RST_SYSTEM 3 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ #define DBCR_EDE 0x02000000 /* Exception Debug Event */ #define DBCR_TDE 0x01000000 /* TRAP Debug Event */ #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ #define DAC_BYTE 0 #define DAC_HALF 1 #define DAC_WORD 2 #define DAC_QUAD 3 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ #define DBCR_SIA 0x00000008 /* Second IAC Enable */ #define DBCR_SDA 0x00000004 /* Second DAC Enable */ #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ #ifndef CONFIG_BOOKE #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #else #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ #endif /* CONFIG_BOOKE */ #ifndef CONFIG_BOOKE #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ #define SPRN_DBSR 0x3F0 /* Debug Status Register */ #else #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ #ifdef CONFIG_BOOKE #define SPRN_DBDR 0x3f3 /* Debug Data Register */ #endif #define SPRN_DBSR 0x130 /* Book E Debug Status Register */ #define DBSR_IC 0x08000000 /* Book E Instruction Completion */ #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ #endif /* CONFIG_BOOKE */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define DCCR_NOCACHE 0 /* Noncacheable */ #define DCCR_CACHE 1 /* Cacheable */ #ifndef CONFIG_BOOKE #define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ #define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ #endif #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ #define DCWR_COPY 0 /* Copy-back */ #define DCWR_WRITE 1 /* Write-through */ #ifndef CONFIG_BOOKE #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ #else #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ #endif /* CONFIG_BOOKE */ #define SPRN_DEC 0x016 /* Decrement Register */ #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ #ifdef CONFIG_BOOKE #define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ #define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ #define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ #define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ #endif #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ #ifdef CONFIG_BOOKE #define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ #define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ #define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ #define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ #define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ #endif #define SPRN_EAR 0x11A /* External Address Register */ #ifndef CONFIG_BOOKE #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ #else #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ #endif /* CONFIG_BOOKE */ #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ #define ESR_PTR 0x02000000 /* Program Exception - Trap */ #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ #define HID0_ICE_SHIFT 15 #define HID0_DCE_SHIFT 14 #define HID0_DLOCK_SHIFT 12 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ #define HID0_SBCLK (1<<27) #define HID0_EICE (1<<26) #define HID0_ECLK (1<<25) #define HID0_PAR (1<<24) #define HID0_DOZE (1<<23) #define HID0_NAP (1<<22) #define HID0_SLEEP (1<<21) #define HID0_DPM (1<<20) #define HID0_ICE (1<> 16) & 0xFFFF) /* Version field */ #define SVR_REV(svr) (((svr) >> 0) & 0xFF) /* Revision field */ #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ /* Processor Version Register */ /* Processor Version Register (PVR) field extraction */ #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ /* * AMCC has further subdivided the standard PowerPC 16-bit version and * revision subfields of the PVR for the PowerPC 403s into the following: */ #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ /* e600 core PVR fields */ #define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ #define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ #define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ #define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ /* Processor Version Numbers */ #define PVR_403GA 0x00200000 #define PVR_403GB 0x00200100 #define PVR_403GC 0x00200200 #define PVR_403GCX 0x00201400 #define PVR_405GP 0x40110000 #define PVR_405GP_RB 0x40110040 #define PVR_405GP_RC 0x40110082 #define PVR_405GP_RD 0x401100C4 #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 #define PVR_405EZ_RA 0x41511460 #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ #define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ #define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ #define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ #define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */ #define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */ #define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */ #define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */ #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 #define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ #define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ #define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ #define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ #define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ #define PVR_440GX_RA 0x51B21850 #define PVR_440GX_RB 0x51B21851 #define PVR_440GX_RC 0x51B21892 #define PVR_440GX_RF 0x51B21894 #define PVR_405EP_RB 0x51210950 #define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ #define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ #define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ #define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ #define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ #define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/ #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ #define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/ #define PVR_460SX_RA 0x13541800 /* 460SX rev A */ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ #define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 #define PVR_603e 0x00060000 #define PVR_603ev 0x00070000 #define PVR_603r 0x00071000 #define PVR_604 0x00040000 #define PVR_604e 0x00090000 #define PVR_604r 0x000A0000 #define PVR_620 0x00140000 #define PVR_740 0x00080000 #define PVR_750 PVR_740 #define PVR_740P 0x10080000 #define PVR_750P PVR_740P #define PVR_7400 0x000C0000 #define PVR_7410 0x800C0000 #define PVR_7450 0x80000000 #define PVR_85xx 0x80200000 #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) #define PVR_VER_E500_V1 0x8020 #define PVR_VER_E500_V2 0x8021 #define PVR_VER_E500MC 0x8023 #define PVR_VER_E5500 0x8024 #define PVR_VER_E6500 0x8040 #define PVR_86xx 0x80040000 #define PVR_VIRTEX5 0x7ff21912 /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be * differentiated by the version number in the Communication Processor * Module (CPM). */ #define PVR_8xx 0x00500000 #define PVR_7400 0x000C0000 /* * MPC 52xx */ #define PVR_5200 0x80822011 #define PVR_5200B 0x80822014 /* * System Version Register */ /* System Version Register (SVR) field extraction */ #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ #ifdef CONFIG_ARCH_MPC8536 #define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/ #else #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ #endif #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ /* Some parts define SVR[0:23] as the SOC version */ #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/ /* whether MPC8xxxE (i.e. has SEC) */ #if defined(CONFIG_MPC85xx) #define IS_E_PROCESSOR(svr) (svr & 0x80000) #else #if defined(CONFIG_MPC83xx) #define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) #endif #endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) /* * SVR_SOC_VER() Version Values */ #define SVR_8533 0x803400 #define SVR_8535 0x803701 #define SVR_8536 0x803700 #define SVR_8540 0x803000 #define SVR_8541 0x807200 #define SVR_8543 0x803200 #define SVR_8544 0x803401 #define SVR_8545 0x803102 #define SVR_8547 0x803101 #define SVR_8548 0x803100 #define SVR_8555 0x807100 #define SVR_8560 0x807000 #define SVR_8567 0x807501 #define SVR_8568 0x807500 #define SVR_8569 0x808000 #define SVR_8572 0x80E000 #define SVR_P1010 0x80F100 #define SVR_P1011 0x80E500 #define SVR_P1012 0x80E501 #define SVR_P1013 0x80E700 #define SVR_P1014 0x80F101 #define SVR_P1017 0x80F700 #define SVR_P1020 0x80E400 #define SVR_P1021 0x80E401 #define SVR_P1022 0x80E600 #define SVR_P1023 0x80F600 #define SVR_P1024 0x80E402 #define SVR_P1025 0x80E403 #define SVR_P2010 0x80E300 #define SVR_P2020 0x80E200 #define SVR_P2040 0x821000 #define SVR_P2041 0x821001 #define SVR_P3041 0x821103 #define SVR_P4040 0x820100 #define SVR_P4080 0x820000 #define SVR_P5010 0x822100 #define SVR_P5020 0x822000 #define SVR_P5021 0X820500 #define SVR_P5040 0x820400 #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 #define SVR_T4160 0x824100 #define SVR_T4080 0x824102 #define SVR_C291 0x850000 #define SVR_C292 0x850020 #define SVR_C293 0x850030 #define SVR_B4860 0X868000 #define SVR_G4860 0x868001 #define SVR_B4460 0x868003 #define SVR_B4440 0x868100 #define SVR_G4440 0x868101 #define SVR_B4420 0x868102 #define SVR_B4220 0x868103 #define SVR_T1040 0x852000 #define SVR_T1041 0x852001 #define SVR_T1042 0x852002 #define SVR_T1020 0x852100 #define SVR_T1021 0x852101 #define SVR_T1022 0x852102 #define SVR_T1024 0x854000 #define SVR_T1023 0x854100 #define SVR_T1014 0x854400 #define SVR_T1013 0x854500 #define SVR_T2080 0x853000 #define SVR_T2081 0x853100 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 #define SVR_8641D 0x809001 #define SVR_9130 0x860001 #define SVR_9131 0x860000 #define SVR_9132 0x861000 #define SVR_9232 0x861400 #define SVR_Unknown 0xFFFFFF #define _GLOBAL(n)\ .globl n;\ n: /* Macros for setting and retrieving special purpose registers */ #define stringify(s) tostring(s) #define tostring(s) #s #define mfdcr(rn) ({unsigned int rval; \ asm volatile("mfdcr %0," stringify(rn) \ : "=r" (rval)); rval;}) #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) #define mfmsr() ({unsigned int rval; \ asm volatile("mfmsr %0" : "=r" (rval)); rval;}) #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) #define mfspr(rn) ({unsigned int rval; \ asm volatile("mfspr %0," stringify(rn) \ : "=r" (rval)); rval;}) #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) /* Segment Registers */ #define SR0 0 #define SR1 1 #define SR2 2 #define SR3 3 #define SR4 4 #define SR5 5 #define SR6 6 #define SR7 7 #define SR8 8 #define SR9 9 #define SR10 10 #define SR11 11 #define SR12 12 #define SR13 13 #define SR14 14 #define SR15 15 #ifndef __ASSEMBLY__ struct cpu_type { char name[15]; u32 soc_ver; u32 num_cores; u32 mask; /* which cpu(s) actually exist */ #ifdef CONFIG_HETROGENOUS_CLUSTERS u32 dsp_num_cores; u32 dsp_mask; /* which DSP cpu(s) actually exist */ #endif }; struct cpu_type *identify_cpu(u32 ver); int fixup_cpu(void); int fsl_qoriq_core_to_cluster(unsigned int core); int fsl_qoriq_dsp_core_to_cluster(unsigned int core); #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v, nc) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \ .mask = (1 << (nc)) - 1 } #define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) } #else #if defined(CONFIG_MPC83xx) #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} #endif #endif struct task_struct; #ifndef CONFIG_CPU_MPC83XX int prt_83xx_rsr(void); #endif #endif /* ndef ASSEMBLY*/ #if defined(CONFIG_MPC85xx) #define EPAPR_MAGIC (0x45504150) #else #define EPAPR_MAGIC (0x65504150) #endif #endif /* __ASM_PPC_PROCESSOR_H */