// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * Copyright : STMicroelectronics 2018 */ #include #include "stm32mp15-u-boot.dtsi" #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" / { aliases { i2c3 = &i2c4; usb0 = &usbotg_hs; }; config { u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; u-boot,mmc-env-partition = "fip"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; #if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL) config { u-boot,mmc-env-partition = "ssbl"; }; #endif #ifdef CONFIG_STM32MP15x_STM32IMAGE /* only needed for boot with TF-A, witout FIP support */ firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; reserved-memory { bootph-pre-ram; optee@de000000 { reg = <0xde000000 0x02000000>; no-map; bootph-pre-ram; }; }; #endif led { red { label = "error"; gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; default-state = "off"; status = "okay"; }; }; }; &adc { status = "okay"; }; &clk_hse { st,digbypass; }; &i2c4 { bootph-all; }; &i2c4_pins_a { bootph-all; pins { bootph-all; }; }; &pmic { bootph-all; }; &rcc { st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P CLK_MCU_PLL3P CLK_PLL12_HSE CLK_PLL3_HSE CLK_PLL4_HSE CLK_RTC_LSE CLK_MCO1_DISABLED CLK_MCO2_DISABLED >; st,clkdiv = < 1 /*MPU*/ 0 /*AXI*/ 0 /*MCU*/ 1 /*APB1*/ 1 /*APB2*/ 1 /*APB3*/ 1 /*APB4*/ 2 /*APB5*/ 23 /*RTC*/ 0 /*MCO1*/ 0 /*MCO2*/ >; st,pkcs = < CLK_CKPER_HSE CLK_FMC_ACLK CLK_QSPI_ACLK CLK_ETH_DISABLED CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE CLK_USBPHY_HSE CLK_SPI2S1_PLL3Q CLK_SPI2S23_PLL3Q CLK_SPI45_HSI CLK_SPI6_HSI CLK_I2C46_HSI CLK_SDMMC3_PLL4P CLK_USBO_USBPHY CLK_ADC_CKPER CLK_CEC_LSE CLK_I2C12_HSI CLK_I2C35_HSI CLK_UART1_HSI CLK_UART24_HSI CLK_UART35_HSI CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q CLK_SAI4_PLL3Q CLK_RNG1_LSI CLK_RNG2_LSI CLK_LPTIM1_PCLK1 CLK_LPTIM23_PCLK3 CLK_LPTIM45_LSE >; /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; reg = <1>; cfg = < 2 65 1 0 0 PQR(1,1,1) >; frac = < 0x1400 >; bootph-all; }; /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ pll3: st,pll@2 { compatible = "st,stm32mp1-pll"; reg = <2>; cfg = < 1 33 1 16 36 PQR(1,1,1) >; frac = < 0x1a04 >; bootph-all; }; /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; cfg = < 3 98 5 7 7 PQR(1,1,1) >; bootph-all; }; }; &sdmmc1 { bootph-pre-ram; }; &sdmmc1_b4_pins_a { bootph-pre-ram; pins1 { bootph-pre-ram; }; pins2 { bootph-pre-ram; }; }; &uart4 { bootph-all; }; &uart4_pins_a { bootph-all; pins1 { bootph-all; }; pins2 { bootph-all; /* pull-up on rx to avoid floating level */ bias-pull-up; }; }; &usbotg_hs { u-boot,force-b-session-valid; };