// SPDX-License-Identifier: GPL-2.0+ // Copyright (C) 2021 Oleh Kravchenko /dts-v1/; #include "imx6ull.dtsi" / { model = "O4-iMX6ULL-NANO"; compatible = "out4,o4-imx6ull-nano", "fsl,imx6ull"; aliases { mmc0 = &usdhc2; }; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; }; }; &iomuxc { pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 >; }; pinctrl_fec1: fec1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 >; }; pinctrl_fec2: fec2grp { fsl,pins = < MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 >; }; pinctrl_phy0_irq: phy0grp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x79 >; }; pinctrl_phy1_irq: phy1grp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 >; }; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; no-1-8-v; non-removable; keep-power-in-suspend; wakeup-source; bus-width = <8>; status = "okay"; };