// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2021 Linumiz * Author: Navin Sankar Velliangiri */ #include #include #include / { model = "Seeed NPi-iMX6ULL Dev Board"; compatible = "fsl,imx6ull"; chosen { stdout-path = &uart1; }; leds { compatible = "gpio-leds"; user-led { label = "User"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpios>; gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; nand-on-flash-bbt; status = "disabled"; }; &uart1 { pinctrl-name = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; no-1-8-v; keep-power-in-suspend; wakeup-source; status = "okay"; }; &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <8>; non-removable; keep-power-in-suspend; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; phy-mode = "rmii"; phy-handle = <ðphy0>; status = "okay"; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rmii"; phy-handle = <ðphy1>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <2>; micrel,led-mode = <1>; clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; micrel,led-mode = <1>; clocks = <&clks IMX6UL_CLK_ENET2_REF>; clock-names = "rmii-ref"; }; }; }; &usbotg1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_otg1_id>; dr_mode = "otg"; srp-disable; hnp-disable; adp-disable; status = "okay"; }; &usbotg2 { dr_mode = "host"; disable-over-current; status = "okay"; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpios>; pinctrl_uart1: uart1grp { fsl,pin = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_usb_otg1_id: usbotg1idgrp { fsl,pin = < MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 >; }; pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 >; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 >; }; pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 >; }; pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 >; }; pinctrl_gpios: gpiosgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 >; }; };