// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * NXP LX2162AQDS device tree source * * Copyright 2020-2021 NXP * */ /dts-v1/; #include "fsl-lx2160a-qds.dtsi" / { model = "NXP Layerscape LX2162AQDS Board"; compatible = "fsl,lx2162aqds", "fsl,lx2160a"; aliases { spi1 = &dspi0; spi2 = &dspi1; spi3 = &dspi2; }; }; &usb1 { status = "disabled"; }; &pcie2 { status = "disabled"; }; &pcie5 { status = "disabled"; }; &pcie6 { status = "disabled"; }; &dspi0 { bus-num = <0>; status = "okay"; dflash0: n25q128a { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; dflash1: sst25wf040b { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; dflash2: en25s64 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <2>; }; }; &dspi1 { bus-num = <0>; status = "okay"; dflash3: n25q128a { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; dflash4: sst25wf040b { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; dflash5: en25s64 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <2>; }; }; &dspi2 { bus-num = <0>; status = "okay"; dflash6: n25q128a { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; dflash7: sst25wf040b { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; dflash8: en25s64 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <2>; }; }; &esdhc1 { mmc-hs200-1_8v; mmc-hs400-1_8v; bus-width = <8>; };